Memory Management for Synthesis of DSP Software focuses on minimizing memory requirements during the synthesis of DSP software from dataflow representations.
Features:
- Focuses on techniques for minimizing memory requirements during the synthesis of software from dataflow representations of DSP systems
- Describes buffer-sharing models and techniques
- Addresses the DSA problem and its various solutions
- Contains an extensive list of references for more in-depth information
- Collects a large amount of SDF compiler work in a single source and explains it coherently and systematically
- Reviews related and background work in the area comprehensivel
Contents
Introduction
- Electronic Embedded Systems
- Digital Signal Processing Systems
- Actor-Oriented Design
- Dataflow MoCs for DSP Systems
- Synthesis Techniques in AOPEs
- Advances in Compilers for DSPs
- Other Related Work-Nested Loop Scheduling
Notation and Background
- Graph Terminology
- Synchronous Dataflow
- Synthesis from SDF Graphs
- Scheduling Problems for SDF Graphs
- Constructing Memory-Efficient Loop Structures
- Scheduling for Other Metrics
- Other Topics: Holes
Lifetime Analysis
- The Shared Buffer Model
- Creating the Interval Instances from a SAS
Dynamic Storage Allocation
- Heuristic for DSA
- Computing the Maximum Clique Weight
- Experimental Results
- Approximation Algorithms
The CBP Parameter
- Introduction to Buffer Merging
- The CBP Parameter
- Multirate FIR Filters
- Chop
- Autocorrelation
- CBP Tables
- Summary of Derivations
Buffer Sharing Via Merging Techniques
- Merging an Input/Output Buffer Pair
- Merging a Chain of Buffers
- A Heuristic for Merged Cost-Optimal SAS
Buffer Merging Algorithms
- Acyclic Graphs
- Experimental Results
Beyond Single Appearance Schedules
- Recursive Decomposition of a Two-Actor SDF Graph
- Extension to Arbitrary SAS
- CD-DAT Example
- Experimental Results
Conclusion
- Regularity
- Fixed-Point Optimizations
- Reconfigurable Systems
- Grand Challenge
Index
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